Intel tips more 0.09-Micron details
ExtremeTech | at | by Mike
Intel Corp. disclosed Tuesday that its 90-nanometer (0.09-micron) process will include a technique called "strained silicon", a process which allows transistor performance to improve without additional process shrinks. In March, Intel executives disclosed that the 90-nm process was already being tested on a 52-Mbit SRAM cell, a simple circuit used to test new process technologies. Intel tipped a few more details on its manufacturing techniques Tuesday, and reiterated that its first 90-nm products would be released in the second half of 2003.
Intel's P1262 90-nm process, as Intel calls it, will include a gate length of less than 50 nm and a gate oxide thickness of 1.2 nm, which Bohr claimed to be the smallest in the industry. Intel will retool its fab in Hillsboro, Ore., later this year to support the new process, followed by its fabs in New Mexico and Ireland. Intel will marry the finer90-nm technology with its largest 300-mm wafer lines, greatly increasing the potential number of microprocessors per wafer. However, the company will not retrofit its 200-mm wafer fabs with the 300-mm technology, Bohr said.